// Copyright (C) 1953-2022 NUDT
// Verilog module name - control_packet_switch_top.v 
// Version: V4.1.0.20221212
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//          
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module control_packet_switch_top
(
        i_clk             ,   
        i_rst_n           ,
        
        i_local_or_remote_ctrl,
        
        iv_data_cpu       ,
        i_data_wr_cpu     , 
        ov_data_cpu       ,        
        o_data_wr_cpu     , 

        iv_data_ta        ,
        i_data_wr_ta      ,    
        ov_data_ta        ,        
        o_data_wr_ta      , 

        iv_data_osc        ,
        i_data_wr_osc      ,    
        ov_data_osc        ,        
        o_data_wr_osc      ,

        iv_data_tse        ,
        i_data_wr_tse      ,    
        ov_data_tse        ,        
        o_data_wr_tse      ,          

        iv_data_tap       ,
        i_data_wr_tap     ,
        
        iv_data_rep       ,
        i_data_wr_rep             
);

// I/O
// clk & rst
input                   i_clk             ;
input                   i_rst_n           ;

input                   i_local_or_remote_ctrl;
                                          
input   [8:0]           iv_data_cpu       ;
input                   i_data_wr_cpu     ; 
output  [8:0]           ov_data_cpu       ; 
output                  o_data_wr_cpu     ; 

input   [8:0]           iv_data_ta        ;
input                   i_data_wr_ta      ; 
output  [8:0]           ov_data_ta        ; 
output                  o_data_wr_ta      ; 

input   [8:0]           iv_data_osc       ;
input                   i_data_wr_osc     ;
output  [8:0]           ov_data_osc       ;
output                  o_data_wr_osc     ;

input   [8:0]           iv_data_tse       ;
input                   i_data_wr_tse     ;
output  [8:0]           ov_data_tse       ;
output                  o_data_wr_tse     ;

input   [8:0]           iv_data_tap       ;
input                   i_data_wr_tap     ;

input   [8:0]           iv_data_rep       ;
input                   i_data_wr_rep     ; 

wire    [8:0]           wv_data_cps12cps3       ;
wire                    w_data_wr_cps12cps3     ;
wire    [8:0]           wv_data_cps32cps1       ;
wire                    w_data_wr_cps32cps1     ;

wire    [8:0]           wv_data_cps42cps5       ;
wire                    w_data_wr_cps42cps5     ;
wire    [8:0]           wv_data_cps52cps4       ;
wire                    w_data_wr_cps52cps4     ;

wire    [8:0]           wv_data_cps32cps5       ;
wire                    w_data_wr_cps32cps5     ;
wire    [8:0]           wv_data_cps52cps3       ;
wire                    w_data_wr_cps52cps3     ;

wire    [8:0]           wv_data_tap_pdi2cps4    ;
wire                    w_data_wr_tap_pdi2cps4  ;
wire    [8:0]           wv_data_tap_pdi2cps3    ;
wire                    w_data_wr_tap_pdi2cps3  ;

wire    [8:0]           wv_data_rep_pdi2cps4    ;
wire                    w_data_wr_rep_pdi2cps4  ;
wire    [8:0]           wv_data_rep_pdi2cps1    ;
wire                    w_data_wr_rep_pdi2cps1  ;

wire    [8:0]           wv_data_tse2cps         ;
wire                    w_data_wr_tse2cps       ;
wire    [8:0]           wv_data_cps2tse         ; 
wire                    w_data_wr_cps2tse       ;
/*
head_and_tail_add head_and_tail_add_cps
(
.i_clk       (i_clk  ),
.i_rst_n     (i_rst_n),

.i_data_wr   (i_data_wr_tse),
.iv_data     (iv_data_tse  ),

.ov_data     (wv_data_tse2cps  ),
.o_data_wr   (w_data_wr_tse2cps)
);

head_and_tail_discard head_and_tail_discard_cps
(
.i_clk      (i_clk  ),
.i_rst_n    (i_rst_n),
          
.iv_data    (wv_data_cps2tse  ),
.i_data_wr  (w_data_wr_cps2tse),
           
.ov_data    (ov_data_tse  ),
.o_data_wr  (o_data_wr_tse)
);
*/
packet_dispatch_1to2 tap_dispatch_1to2_inst
(
    .i_clk        (i_clk                 ),
    .i_rst_n      (i_rst_n               ),
	                          
	.i_ctrl       (i_local_or_remote_ctrl),//1'b0:local;  1'b1:remote
                             
    .iv_data      (iv_data_tap       ),
	.i_data_wr    (i_data_wr_tap     ),
                          
	.ov_data_0    (wv_data_tap_pdi2cps4  ),//1'b0:local 
	.o_data_wr_0  (w_data_wr_tap_pdi2cps4),
                      
	.ov_data_1    (wv_data_tap_pdi2cps3  ),//1'b1:remote
	.o_data_wr_1  (w_data_wr_tap_pdi2cps3)    
);

packet_dispatch_1to2 report_dispatch_1to2_inst
(
    .i_clk        (i_clk                 ),
    .i_rst_n      (i_rst_n               ),
	                          
	.i_ctrl       (i_local_or_remote_ctrl),//1'b0:local;  1'b1:remote
                             
    .iv_data      (iv_data_rep       ),
	.i_data_wr    (i_data_wr_rep     ),
                          
	.ov_data_0    (wv_data_rep_pdi2cps4  ),//1'b0:local 
	.o_data_wr_0  (w_data_wr_rep_pdi2cps4),
                      
	.ov_data_1    (wv_data_rep_pdi2cps1  ),//1'b1:remote
	.o_data_wr_1  (w_data_wr_rep_pdi2cps1)    
);

control_packet_switch tse_interface_switch//cds1
(
        .i_clk           (i_clk      ),   
        .i_rst_n         (i_rst_n    ),
                                     
        .iv_data_0       (wv_data_cps32cps1  ),
        .i_data_wr_0     (w_data_wr_cps32cps1),
        .ov_data_0       (wv_data_cps12cps3  ),        
        .o_data_wr_0     (w_data_wr_cps12cps3), 
                                     
        .iv_data_1       (iv_data_osc  ),
        .i_data_wr_1     (i_data_wr_osc),
        .ov_data_1       (ov_data_osc  ),        
        .o_data_wr_1     (o_data_wr_osc),  
                                     
        .iv_data_2       (wv_data_rep_pdi2cps1  ),
        .i_data_wr_2     (w_data_wr_rep_pdi2cps1),
        //.ov_data_2       (  ),        
        //.o_data_wr_2     (  ),

        .iv_data_3       (iv_data_tse  ),//(wv_data_tse2cps  ),
        .i_data_wr_3     (i_data_wr_tse),//(w_data_wr_tse2cps),
        .ov_data_3       (ov_data_tse  ),//(wv_data_cps2tse  ),        
        .o_data_wr_3     (o_data_wr_tse) //(w_data_wr_cps2tse)          
);

control_packet_switch tse_tap_ta_switch//cps3
(
        .i_clk           (i_clk      ),   
        .i_rst_n         (i_rst_n    ),
                                     
        .iv_data_0       (wv_data_cps12cps3  ),
        .i_data_wr_0     (w_data_wr_cps12cps3),
        .ov_data_0       (wv_data_cps32cps1  ),        
        .o_data_wr_0     (w_data_wr_cps32cps1), 
                                     
        .iv_data_1       (wv_data_tap_pdi2cps3  ),
        .i_data_wr_1     (w_data_wr_tap_pdi2cps3),
        .ov_data_1       (                  ),        
        .o_data_wr_1     (                  ), 

        .iv_data_2       (9'b0              ),
        .i_data_wr_2     (1'b0              ),
        //.ov_data_2       (  ),        
        //.o_data_wr_2     (  ),        
                                     
        .iv_data_3       (wv_data_cps52cps3  ),
        .i_data_wr_3     (w_data_wr_cps52cps3),
        .ov_data_3       (wv_data_cps32cps5  ),        
        .o_data_wr_3     (w_data_wr_cps32cps5)         
);

control_packet_switch cpu_interface_switch//cps4
(
        .i_clk           (i_clk      ),   
        .i_rst_n         (i_rst_n    ),
                                     
        .iv_data_0       (wv_data_cps52cps4  ),
        .i_data_wr_0     (w_data_wr_cps52cps4),
        .ov_data_0       (wv_data_cps42cps5  ),        
        .o_data_wr_0     (w_data_wr_cps42cps5), 
                                     
        .iv_data_1       (wv_data_tap_pdi2cps4  ),
        .i_data_wr_1     (w_data_wr_tap_pdi2cps4),
        .ov_data_1       (             ),        
        .o_data_wr_1     (             ),

        .iv_data_2       (wv_data_rep_pdi2cps4              ),
        .i_data_wr_2     (w_data_wr_rep_pdi2cps4            ),
        //.ov_data_2       (  ),        
        //.o_data_wr_2     (  ),            
                                     
        .iv_data_3       (iv_data_cpu  ),
        .i_data_wr_3     (i_data_wr_cpu),
        .ov_data_3       (ov_data_cpu  ),        
        .o_data_wr_3     (o_data_wr_cpu)          
);

tsmp_packet_switch tsmp_interface_switch//cps5
(
        .i_clk           (i_clk      ),   
        .i_rst_n         (i_rst_n    ),
        
        .i_local_or_remote_ctrl(i_local_or_remote_ctrl),
        
        .iv_data_0       (wv_data_cps42cps5      ),
        .i_data_wr_0     (w_data_wr_cps42cps5    ),
        .ov_data_0       (wv_data_cps52cps4      ),        
        .o_data_wr_0     (w_data_wr_cps52cps4    ), 
                                     
        .iv_data_1       (wv_data_cps32cps5  ),
        .i_data_wr_1     (w_data_wr_cps32cps5),
        .ov_data_1       (wv_data_cps52cps3  ),        
        .o_data_wr_1     (w_data_wr_cps52cps3),  

        .iv_data_2       (9'b0              ),
        .i_data_wr_2     (1'b0              ),
        //.ov_data_2       (  ),        
        //.o_data_wr_2     (  ), 
        
        .iv_data_3       (iv_data_ta         ),
        .i_data_wr_3     (i_data_wr_ta       ),
        .ov_data_3       (ov_data_ta         ),        
        .o_data_wr_3     (o_data_wr_ta       )          
);
endmodule